SH7764 Datasheet, PDF (41/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 24.6 Data Enable Signals ................................................................................................. 1232
Figure 24.7 Pixel Bus Endian (ENDIAN = 0) ............................................................................. 1241
Figure 24.8 Pixel Bus Endian (ENDIAN = 1) ............................................................................. 1242
Figure 24.9 Graphic Image Area Settings (Reading from Memory) ........................................... 1244
Figure 24.10 Graphic Image Memory Area Settings................................................................... 1245
Figure 24.11 α Control Area Settings ......................................................................................... 1248
Figure 24.12 Screen Format ........................................................................................................ 1254
Figure 24.13 COM Signal Timing............................................................................................... 1268
Figure 24.14 Settings of DE Area Generated in SG Block.......................................................... 1269
Figure 24.15 T-1004 Video Output Position ............................................................................... 1274
Section 25 NAND Flash Memory Controller (FLCTL)
Figure 25.1 FLCTL Block Diagram ............................................................................................ 1280
Figure 25.2 Register Setting Flow............................................................................................... 1307
Figure 25.3 Read Operation Timing for NAND-Type Flash Memory (1) .................................. 1308
Figure 25.4 Programming Operation Timing for NAND-Type Flash Memory (1)..................... 1309
Figure 25.5 Programming Operation Timing for NAND-Type Flash Memory (2)..................... 1309
Figure 25.6 Read Operation Timing for NAND-Type Flash Memory ........................................ 1310
Figure 25.7 Programming Operation Timing for NAND-Type Flash Memory (1)..................... 1310
Figure 25.8 Programming Operation Timing for NAND-Type Flash Memory (2)..................... 1311
Figure 25.9 Relationship between DMA Transfer and Sector (Data and Control Code), and
Memory and DMA Transfer .................................................................................... 1312
Figure 25.10 Relationship between Sector Number and Address Expansion of
NAND-Type Flash Memory .................................................................................. 1313
Figure 25.11 Sector Access when Unusable Sector Exists in Continuous Sectors...................... 1314
Section 26 Sampling Rate Converter (SRC)
Figure 26.1 Block Diagram of SRC ............................................................................................ 1318
Figure 26.2 Sample Flowchart for Initial Setting ........................................................................ 1331
Figure 26.3 Sample Flowchart for Data Input ............................................................................. 1332
Figure 26.4 Sample Flowchart for Data Output .......................................................................... 1333
Section 28 Power-Down Mode
Figure 28.1 STATUS Output when an Interrupt Occurs in Sleep Mode ..................................... 1423
Section 29 Watchdog Timer and Reset
Figure 29.1 Block Diagram ......................................................................................................... 1426
Figure 29.2 WDT Counting Operations (Example in Interval Timer Mode) .............................. 1435
Figure 29.3 STATUS Output during Power-on........................................................................... 1437
Figure 29.4 STATUS Output by Reset input during Normal Operation ..................................... 1438
Figure 29.5 STATUS Output by Reset input during Sleep Mode ............................................... 1438
Rev. 1.00 Nov. 22, 2007 Page xli of lvi