SH7764 Datasheet, PDF (322/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.4.1 Version Control Register (VCR)
Bit: 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48

Initial value: 0
0
0
0
1
0
1
1
0
0
0
0
0
1
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0






DRAM_ DRAM_
SELFREF INACTIVE


BAD_
OPC



ERR_
SNT

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R R R/W R R R R/W R
Initial
Bit
Bit Name Value R/W
63 to 10 
0/1
R
9
DRAM_ 0
R/W
SELFREF
8
DRAM_ 0
R/W
INACTIVE
Description
Reserved
These bits always return the initial values shown in the
bit map above. The write value should always be 0.
This bit is set to 1 when a data block area is accessed
while self-refresh mode is enabled by the RMODE,
DRE, and DCE bits in MIM. This bit is cleared by
writing 0 to it.
This bit is set to 1 when a data block area is accessed
while the SDRAM controller is disabled by the DCE bit
in MIM. This bit is cleared by writing 0 to it.
Rev. 1.00 Nov. 22, 2007 Page 266 of 1692
REJ09B0360-0100