SH7764 Datasheet, PDF (393/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
11.7.8 Refresh
(1) Auto-Refresh
The auto-refresh interval is specified by the DRI[11:00] bits in MIM. If the DRE bit is set to 1 at
the same time as the DRI bits are set, the time until the first auto-refresh is determined by the
value of the DRI bits before the new setting was made. However, the second and subsequent auto-
refresh intervals are determined by the value corresponding to the new setting for the DRI bits. To
avoid this situation, clear the DRE bit to 0 when setting the DRI bits. When the DRE bit is
subsequently set to 1, auto-refreshing proceeds with the specified interval from the first round.
When writing 1 to the DRE bit, the previously written cycle number should be set to the DRI bits.
Note that when the MIM register is not set so that the counter for the auto-refresh function starts
operating, the delay adjustment unit in the MCU does not work correctly, thus disabling correct
SDRAM read access. Therefore, be sure to set the MIM register appropriately to enable the auto-
refresh function before making a read access to SDRAM, as described in the SDRAM
initialization sequence and the recovery sequence from the self-refresh state in this specifications
document.
When SDRAM auto-refresh occurs during SRAM access by the LBSC, the ARBT module gives
priority to auto-refresh and masks the next SRAM access request that has been already accepted.
In this case, the next request is sent to the LBSC when the specified idle cycles have been passed
after auto-refresh completion. This also applies to the case in which the next request is an SDRAM
access.
(2) Self-Refresh
[Transition to self-refresh state]
1. Confirm that the transaction to the memory controller is completed.
2. Through software control, set the SMS[2:0] bits in SCR to issue the PALL (precharge select
all bank) command. This closes any SDRAM bank that was open. After that, use the SMS[2:0]
bits in SCR to issue the CBR (auto-refresh) command to perform concentrated refresh on all
memory rows (CBR).
3. To make the SDRAM enter the self-refresh state, set the DRE and RMODE bits in MIM in the
SBSC to 1. In this case, the BW[1:0] bits should remain 10 and the DCE bit should remain 1.)
4. The memory controller automatically issues the self-refresh command and sets the external
CKE pin low. The SDRAM then automatically enters power-down mode.
5. Whether the SDRAM has entered self-refresh mode can be checked by reading the SELFS bit
in MIM.
Rev. 1.00 Nov. 22, 2007 Page 337 of 1692
REJ09B0360-0100