SH7764 Datasheet, PDF (297/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 On-Chip Memory
9.3 Operation
9.3.1 Instruction Fetch Access from the CPU
Instruction fetch access from the CPU is performed directly via the instruction bus for a given
virtual address. In the case of successive accesses to the same page of IL memory and as long as
no page conflict occurs, the access takes one cycle.
9.3.2 Operand Access from the CPU and Access from the FPU
Operand access from the CPU and access from the FPU are performed via the cache/RAM internal
bus. Access via the cache/RAM internal bus takes more than one cycle.
Note: Operand access is applied for PC relative access (@(disp,pc)).
9.3.3 Access from the SuperHyway Bus Master Module
On-chip memory is always accessed by the SuperHyway bus master module, such as DMAC, via
the SuperHyway bus which is a physical address bus. The same addresses as for the virtual
addresses must be used.
Rev. 1.00 Nov. 22, 2007 Page 241 of 1692
REJ09B0360-0100