SH7764 Datasheet, PDF (1278/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
Item
Function
Output video format RGB666 progressive video output (each of RGB colors is represented by
6 bits: 18 bits in total)
8-bit digital video output conforming to BTA T-1004 (parallel interface in
the 8:4:4 bit format)
(the RGB data output timing can be set to the rising or falling edge of the
clock through the SYNCNT register setting)
Sync signal output
Either a combination of Vsync, Hsync, data enable, and COM/CDE
signals, or a combination of SPL, CLS, SPS, data enable, and COM/CDE
signals can be selected (each signal output timing can be set to the rising
or falling edge of the clock and the polarity can be selected through the
SYNCNT register setting).
External sync mode
The VDC2 can operate with external sync signals (EX-VSYNC and EX-
HSYNC) and the panel clock (the external sync signal timing can be set to
the rising or falling edge of the clock and the polarity can be selected
through the SYNCNT register setting).
Note that only RGB666 video data can be output in this mode.
Chroma enable signal Outputs a chroma data enable (CDE) signal for the specified color in the
output
video image.
Rev. 1.00 Nov. 22, 2007 Page 1222 of 1692
REJ09B0360-0100