SH7764 Datasheet, PDF (1303/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
Initial
Bit
Bit Name Value
R/W Description
31 to 26 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 16 GROPEH H'000
[9:0]
R/W These bits specify the height of the α control area
in number of lines.
15 to 10 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 0
GROPEW H'000
[9:0]
R/W These bits specify the width of the α control area in
number of panel clock cycles.
Note: Layer 1 is the bottom image which has no α control target, so the above settings are
prohibited for layer 1.
Each register specifies the size of the α control area (rectangle). See figure 24.11.
24.6.8 α Control Area Start Position Registers (GROPEDPHV2 to GROPEDPHV4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16






GROPEDPV[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0






GROPEDPH[9:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 1247 of 1692
REJ09B0360-0100