SH7764 Datasheet, PDF (1579/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 32 List of Registers
Module
Register Name
P4 Area
Abbreviation R/W Address*
Area 7
Address*
Access
Size Remarks
SSI_CH0 to 5 Control register 2
Status register 2
SSICR2
SSISR2
R/W H'FF40 4000 H'1F40 4000 32
R/W*⁸ H'FF40 4004 H'1F40 4004 32
Transmit data register 2 SSITDR2
R/W H'FF40 4008 H'1F40 4008 32
Receive data register 2 SSIRDR2
R
H'FF40 400C H'1F40 400C 32
Control register 3
SSICR3
R/W H'FF50 2000 H'1F50 2000 32
Status register 3
SSISR3
R/W*⁸ H'FF50 2004 H'1F50 2004 32
Transmit data register 3 SSITDR3
R/W H'FF50 2008 H'1F50 2008 32
Receive data register 3 SSIRDR3
R
H'FF50 200C H'1F50 200C 32
Control register 4
SSICR4
R/W H'FF50 3000 H'1F50 3000 32
Status register 4
SSISR4
R/W*⁸ H'FF50 3004 H'1F50 3004 32
Transmit data register 4 SSITDR4
R/W H'FF50 3008 H'1F50 3008 32
Receive data register 4 SSIRDR4
R
H'FF50 300C H'1F50 300C 32
Control register 5
Status register 5
SSICR5
SSISR5
R/W H'FF50 4000 H'1F50 4000 32
R/W*⁸ H'FF50 4004 H'1F50 4004 32
Transmit data register 5 SSITDR5
R/W H'FF50 4008 H'1F50 4008 32
Receive data register 5 SSIRDR5
R
H'FF50 400C H'1F50 400C 32
EtherC
EtherC mode register ECMR
R/W H'FEF0 0100* H'1EF0 0100* 32
EtherC status register ECSR
R/W H'FEF0 0110* H'1EF0 0110* 32
EtherC interrupt
permission register
ECSIPR
R/W H'FEF0 0118* H'1EF0 0118* 32
Receive frame length
register
RFLR
R/W H'FEF0 0108* H'1EF0 0108* 32
PHY interface register PIR
R/W H'FEF0 0120* H'1EF0 0120* 32
MAC address high
register
MAHR
R/W H'FEF0 01C0* H'1EF0 01C0* 32
MAC address low
register
MALR
R/W H'FEF0 01C8* H'1EF0 01C8* 32
PHY status register
PSR
R
H'FEF0 0128* H'1EF0 0128* 32
Transmit retry over
counter register
TROCR
R/W H'FEF0 01D0* H'1EF0 01D0* 32
Delayed collision detect CDCR
counter register
R/W H'FEF0 01D4* H'1EF0 01D4* 32
Rev. 1.00 Nov. 22, 2007 Page 1523 of 1692
REJ09B0360-0100