SH7764 Datasheet, PDF (21/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

19.3.17 Residual-Bit Frame Receive Counter Register (RFCR) ....................................... 725
19.3.18 Multicast Address Frame Receive Counter Register (MAFCR)........................... 726
19.3.19 IPG Register (IPGR)............................................................................................. 727
19.3.20 Automatic PAUSE Frame Register (APR) ........................................................... 728
19.3.21 Manual PAUSE Frame Register (MPR) ............................................................... 729
19.3.22 Automatic PAUSE Frame Retransmit Count Register (TPAUSER) .................... 730
19.3.23 Random Number Generation Counter Upper Limit Setting Register
(RDMLR) ............................................................................................................. 731
19.3.24 PAUSE Frame Receive Counter Register (RFCF) ............................................... 732
19.3.25 PAUSE Frame Retransmit Counter Register (TPAUSECR) ................................ 733
19.3.26 Broadcast Frame Receive Count Setting Register (BCFRR)................................ 734
19.4 Operation ........................................................................................................................... 735
19.4.1 Transmission......................................................................................................... 735
19.4.2 Reception .............................................................................................................. 737
19.4.3 MII Frame Timing ................................................................................................ 739
19.4.4 Accessing MII Registers ....................................................................................... 741
19.4.5 Magic Packet Detection ........................................................................................ 744
19.4.6 Operation by IPG Setting...................................................................................... 745
19.4.7 Flow Control......................................................................................................... 745
19.5 Connection to LSI .............................................................................................................. 747
19.6 Usage Notes ....................................................................................................................... 748
Section 20 Ethernet Controller Direct Memory Access Controller
(E-DMAC) .......................................................................................749
20.1 Features.............................................................................................................................. 749
20.2 Register Descriptions ......................................................................................................... 751
20.2.1 E-DMAC Mode Register (EDMR) ....................................................................... 753
20.2.2 E-DMAC Transmit Request Register (EDTRR)................................................... 754
20.2.3 E-DMAC Receive Request Register (EDRRR) .................................................... 755
20.2.4 Transmit Descriptor List Start Address Register (TDLAR) ................................. 756
20.2.5 Receive Descriptor List Start Address Register (RDLAR)................................... 757
20.2.6 E-MAC/E-DMAC Status Register (EESR) .......................................................... 758
20.2.7 E-MAC/E-DMAC Status Interrupt Permission Register (EESIPR) ..................... 763
20.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 766
20.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 769
20.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 770
20.2.11 FIFO Depth Register (FDR) ................................................................................. 772
20.2.12 Receiving Method Control Register (RMCR) ...................................................... 773
20.2.13 Transmit FIFO Underrun Counter (TFUCR)........................................................ 775
20.2.14 Receive FIFO Overflow Counter (RFOCR) ......................................................... 776
Rev. 1.00 Nov. 22, 2007 Page xxi of lvi