SH7764 Datasheet, PDF (51/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 18.4
Table 18.5
Table 18.6
Table 18.7
Table 18.8
Table 18.9
SSI_DMAC1 Register Configuration ................................................................... 626
SSI_DMAC1 Register State in Each Operating Mode ......................................... 628
Register Configuration of SSI_CH0 to SSI_CH5 ................................................. 631
Register State in Each Operating Mode for SSI_CH0 to SSI_CH5...................... 632
Bus Formats of SSI Module.................................................................................. 680
Number of Padding Bits for Each Valid Configuration........................................ 684
Section 19 Ethernet Controller (EtherC)
Table 19.1 Pin Configuration.................................................................................................. 702
Table 19.2 Register Configuration.......................................................................................... 703
Table 19.3 Register States in Each Operation Mode .............................................................. 704
Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Table 20.1 Register Configuration.......................................................................................... 751
Table 20.2 Register States in Each Operating Mode .............................................................. 752
Section 21 USB 2.0 Host/Function Module (USB)
Table 21.1 USB Pin Configuration ......................................................................................... 804
Table 21.2 Register Configuration.......................................................................................... 805
Table 21.3 Register State in Each Processing Mode............................................................... 808
Table 21.4 Register Bits Initialized by Writing USBE = 0 (when Function Controller
Function is Selected)............................................................................................. 814
Table 21.5 Register Bits Initialized by Writing USBE = 0
(when Host Controller Function is Selected) ........................................................ 814
Table 21.6 USB Data Bus Line Status.................................................................................... 817
Table 21.7 Test Mode Operation ............................................................................................ 825
Table 21.8 Endian Operation in 32-Bit Access (when MBW = 10) ....................................... 828
Table 21.9 Endian Operation in 16-Bit Access (when MBW = 01) ....................................... 829
Table 21.10 Endian Operation in 8-Bit Access (when MBW = 00) ..................................... 829
Table 21.11 Meaning of BSTS Bit........................................................................................ 915
Table 21.12 Information Cleared by this Module by Setting ACLRM = 1 .......................... 916
Table 21.13 Operation of This Module depending on PID Setting
(when Host Controller Function is Selected) .................................................... 916
Table 21.14 Operation of This Module depending on PID Setting
(when Function Controller Function is Selected) ............................................. 917
Table 21.15 Information Cleared by this Module by Setting ACLRM = 1 .......................... 926
Table 21.16 Types of Reset .................................................................................................. 933
Table 21.17 Interrupt Generation Conditions ....................................................................... 936
Table 21.18 Pipe Setting Items ............................................................................................. 960
Table 21.19 Buffer Status Indicated by the BSTS Bit .......................................................... 971
Table 21.20 Buffer Status Indicated by the INBUFM Bit .................................................... 971
Table 21.21 List of Buffer Clearing Methods....................................................................... 972
Rev. 1.00 Nov. 22, 2007 Page li of lvi