SH7764 Datasheet, PDF (404/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Memory Controller Unit (MCU)
The specific sequence of bus recovery from a slave is described below. On detecting BREQ
negation at the rising edge of the clock pulse, BACK is immediately negated and the bus control
signals begin to be driven simultaneously. The address bus also begins to be driven at the rising
edge of the same clock pulse. The fastest timing at which bus access can be resumed is at the
rising edge of the clock pulse that is one clock cycle after the cycle at which the bus control
signals began to be driven.
Before starting refreshing operation or bus access execution after bus recovery, BREQ should be
negated for two or more clock cycles.
When a refresh request is issued while BACK is asserted and the bus is released, BACK is
negated in order to request the slave to release the bus even while BREQ is asserted. With the
user-designed slave, multiple bus accesses may be generated consecutively to reduce the overhead
due to arbitration. When the slave is to be connected such that the total time of the consecutive
accesses exceeds the specified refresh interval, the slave should be designed so that it releases the
bus as soon as BACK negation is detected.
Also, when a bus access request is issued from an internal bus master while the bus is released, it
is not accepted until the bus mastership is recovered. In this case, however, BACK is not negated
and a bus release is not requested. When the bus mastership is recovered in response to a memory
refresh request issued, and any requests from internal bus masters are in queue for acceptance at
that time, refreshing is immediately followed by execution of these bus accesses. Therefore, the
bus may not be released until the accepted bus accesses have been completed even when the slave
immediately issues the bus request again.
CLKOUT
BREQ
BACK
A25 to A0
CSn
R/W
RD
WE
D63 to D0
BS
Asserted for at
least 2 cycles
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Negated
within 2 cycles
Master access
Slave access
Figure 11.23 Arbitration Sequence
Rev. 1.00 Nov. 22, 2007 Page 348 of 1692
REJ09B0360-0100
Master access