SH7764 Datasheet, PDF (684/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Channel Register Name
Abbreviation R/W
Common DMA operation register SSIDMAOR1 R/W
to 3 to 5 1
Interrupt status register SSIDMINTSR1 R/W
1
Interrupt mask register 1 SSIDMINTMR1 R/W
Area P4
Address
H'FF50 1180
H'FF50 1188
H'FF50 1190
Area 7
Address
Access
Size
H'1F50 1180 32
H'1F50 1188 32
H'1F50 1190 32
Table 18.5 SSI_DMAC1 Register State in Each Operating Mode
Channel Register Name
3
DMA mode register 3
RDMA transfer source
address register 3
RDMA transfer word
count register 3
WDMA transfer
destination address
register 3
WDMA transfer word
count register 3
DMA control register 3
Transmit suspension
block counter 3
Transmit suspension
transfer data register 3
Block count source
register 3
Block counter 3
n-times block transfer
interrupt count source
register 3
n-times block counter 3
4
DMA mode register 4
RDMA transfer source
address register 4
Abbreviation
SSIDMMR3
SSIRDMADR3
SSIRDMCNTR3
SSIWDMADR3
SSIWDMCNTR3
SSIDMCOR3
SSISTPBLCNT3
SSISTPDR3
SSIBLCNTSR3
SSIBLCNT3
SSIBLNCNTSR3
SSIBLNCNT3
SSIDMMR4
SSIRDMADR4
Power-On
Reset
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
H'0000 0000
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev. 1.00 Nov. 22, 2007 Page 628 of 1692
REJ09B0360-0100