SH7764 Datasheet, PDF (478/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.3 Interrupt Priority Register (INTPRI)
INTPRI is a 32-bit readable/writable register that sets the IRQ1 and IRQ0 interrupt priorities
(levels 15 to 0).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP0
IP1
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 28 IP0
H'0
R/W Set priority of an independent interrupt request of IRQ0.
27 to 24 IP1
H'0
R/W Set priority of an independent interrupt request of IRQ1.
23 to 0 
All0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Interrupt priorities should be determined by setting a value from H'F to H'1 to each 4-bit field. If
the value is larger, the priority is higher. When the value of H'0 is set to a field, a corresponding
interrupt is masked (initial value).
Rev. 1.00 Nov. 22, 2007 Page 422 of 1692
REJ09B0360-0100