SH7764 Datasheet, PDF (636/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 I²C Bus Interface
16.4.9 Master Receive Operation
The data receive procedure and operation in master receive mode are described below. Figure
16.10 shows the timing chart in master receive mode. Setting the MDBS bit in the master control
register allows the IIC to operate in single-buffer mode.
1. In master receive mode, as to transmit of a slave address and a 1-bit signal indicating the data
transfer direction, operation is the same as that in master transmit mode. At this time, set the
data transfer direction to 1 (reception).
2. The slave device automatically enters the data transmit mode according to the signal that
indicates the data transfer direction, and transmits 1-byte data in synchronization with the SCL
clock output from the master device. The master device generates an interrupt of MDR (bit 1)
at the eighth clock (at the timing of (2) in figure 11). Clear the MDR bit after the master device
reads receive data. If this processing is delayed, the slave device extends the SCL period to
suspend data transmission, as shown at the timing of (3) in figure 16.10.
3. The slave device generates an interrupt of the status SDT (bit 2) indicating 1-byte data transfer
end at the eighth clock (at the timing of (2) in figure 16.10) and an interrupt of the status SDE
(bit 3) indicating data empty at the ninth clock (at the timing of (1) in figure 16.10). Clear SDE
after writing slave transmit data to TXD.
4. To end data transfer, set FSB (bit 1) in the master control register of the master device and
output suspend condition. After the IIC module fetches FSB on completion of transmission or
reception of the last of byte data, it enters the stop state. . Therefore in order to stop the
communication after predetermined number of byte data is transferred, FSB bit needs to be set
before the last byte data transfer is started. After confirmation of the last byte data reception,
though the master receiver finishes the receive transaction, the protocol layer will inform the
slave transmitter or retransmission if the last byte is incorrect.
Signal level changes of (1) to (3) in figure 16.10 are generated after the falling edge of the clock.
Rev. 1.00 Nov. 22, 2007 Page 580 of 1692
REJ09B0360-0100