SH7764 Datasheet, PDF (650/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.2 ATAPI Status (ATAPI_STATUS)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
— SWERR IFERR DNEND DEVTRM DEVINT TOUT ERR NEND ACT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/WC0 R/WC0 R/WC0 R/WC0 R R/WC0 R/WC0 R/WC0 R
Bit
31 to 9
8
7
6
5
Initial
Bit Name Value
—
All 0
SWERR 0
IFERR 0
DNEND 0
DEVTRM 0
R/W
R
R/WC0
R/WC0
R/WC0
R/WC0
Description
Reserved
SWERR is a software error. It indicates that Task File
register access is detected while DMA is active. It is
prohibited. For example, this bit is set to 1 if PIO transfer
is performed during the transfer of the Ultra DMA or
multiword DMA. In this case, no output is sent to the
outside of the LSI so that access is ignored
Writing 0 resets this register.
IFERR indicates that an ATAPI interface protocol error is
detected. In other words,
1. (IODREQ = 1) or (IDEIORDY = 0) when the ULTRA
DMA data-in burst is in the host termination.
2. IDEIORDY = 0 when the ULTRA DMA data-out burst
is in the device termination.
3. IDEIORDY = 0 when the ULTRA DMA data-out burst
is initiated.
4. (IODREQ = 1) or (IDEIORDY = 0) when the ULTRA
DMA data-out burst is in the host termination.
Writing 0 resets this register.
DNEND indicates that all DMAs have been successfully
terminated in the descriptor mode. Writing 0 resets this
register.
DEVTRM is set to 1 when the ATAPI device is
terminated in the Ultra DMA mode before the number of
DMA transfer bytes reach the value set in this ATAPI
module. Writing 0 resets this register.
Rev. 1.00 Nov. 22, 2007 Page 594 of 1692
REJ09B0360-0100