SH7764 Datasheet, PDF (915/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 21 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
14
BCHG
0
R/W*¹ USB Bus Change Interrupt Status
Indicates the status of the USB bus change interrupt.
0: BCHG interrupts not generated
1: BCHG interrupts generated
This module detects the BCHG interrupt when a
change in the full-speed signal level occurs on the
USB port (a change from J-state, K-state, or SE0 to
J-state, K-state, or SE0), and sets this bit to 1. Here,
if software has set the corresponding interrupt enable
bit to 1, this module generates the interrupt.
This module sets the LNST bits in SYSSTS0 to
indicate the current input state of the USB port.
When the BCHG interrupt is generated, use software
to repeat reading the LNST bits until the same value
is read three or more times, and eliminate chattering.
A change in the USB bus state can be detected even
while the internal clock supply is stopped.
When the function controller function is selected, the
read value is invalid.
13

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 859 of 1692
REJ09B0360-0100