SH7764 Datasheet, PDF (693/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
18.3.4 WDMA Transfer Destination Address Registers 0 to 5 (SSIWDMADR0 to
SSIWDMADR5)
SSIWDMADR0 to SSIWDMADR5 is a 32-bit readable/writable register that set the transfer
destination memory address during WDMA transfer other than the port function. This register
value is initialized when either of the conditions is implemented such as hardware reset, software
reset or software reset for SSI_DMAC (DMRST bit in SSIDMACOR0 to SSIDMACOR3). To be
written to this register, DMEN bit in SSIDMCOR0 to SSDMCOR5 must be 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDMADR[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
WDMADR[15:3]



Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 3 WDMADR All 0
[31:3]
R/W WDMA Transfer Source Address
These bits set the data transfer destination memory
address during WDMA transfer.
2 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
18.3.5 WDMA Transfer Word Count Registers 0 to 5 (SSIWDMCNTR0 to
SSIWDMCNTR5)
SSIWDMCNTR0 to SSIWDMCNTR5 is a 32-bit readable/writable register that set data transfer
word count (number of bytes) during WDMA transfer other than the port function. This register
value is initialized when either of the conditions is implemented such as hardware reset, software
reset or software reset for SSI_DMAC (DMRST bit in SSIDMACOR0 to SSIDMACOR3). To be
written to this register, DMEN bit in SSIDMCOR0 to SSDMCOR5 must be 0.
Rev. 1.00 Nov. 22, 2007 Page 637 of 1692
REJ09B0360-0100