SH7764 Datasheet, PDF (1494/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Watchdog Timer and Reset
EXTAL
input
CLKOUT
output
PRESET
input
STATUS[1:0]
output
LL (normal)
HH (reset)
LL (normal)
Reset holding time
PLL synchronization
settling time
Figure 29.4 STATUS Output by Reset input during Normal Operation
PRESET input during Sleep Mode
It is necessary to ensure the PLL oscillation time when power-on reset generates by the PRESET
pin low revel input during sleep mode.
The STATUS [1:0] pins output timing that indicates the reset state is asynchronous, and that
indicates a normal operation is synchronous with the peripheral clock (Pck) and asynchronous
with both the EXTAL pin input clock and the CLKOUT pin output clock.
EXTAL
input
CLKOUT
output
PRESET
input
STATUS[1:0]
output
HL (sleep)
HH (reset)
LL (normal)
Reset holding time
PLL synchronization
settling time
Figure 29.5 STATUS Output by Reset input during Sleep Mode
Rev. 1.00 Nov. 22, 2007 Page 1438 of 1692
REJ09B0360-0100