SH7764 Datasheet, PDF (668/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.5 Operating Procedure
17.5.1 Initialization
(1) Setting of Interface Enable Bit
Set the IFEN bit of the ATAPI control 2 register to 1.
(2) Setting of Timing Registers
Write appropriate values to the following registers.
For details, refer to register descriptions.
• PIO timing register
• Multiword DMA timing register
• Ultra DMA timing register
17.5.2 Procedure in PIO Transfer Mode
• Case Not Using FIFO
Start
No
Master Drive?
Yes
Write 1 to M/S bit of ATAPI control
register.
Write 0 to M/S bit of ATAPI control
register.
Write or read task file registers.
End
Note: Do not execute PIO transfer while the ACT bit in the ATAPI status register is 1.
Figure 17.6 Procedure in PIO Transfer Mode
Rev. 1.00 Nov. 22, 2007 Page 612 of 1692
REJ09B0360-0100