SH7764 Datasheet, PDF (1648/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 33 Electrical Characteristics
CLKOUT
BANK
Precharge
Address
CSn
R/W
RAS
CAS
DQMn
D63 to D0
(Read)
BS
CKE
DACKn
(Low-active)
DTENDn
(Low-active)
Tpr
Tpc
Tr
Trw
Tc1
Tc2
Td1
Td2
Td3 Td4
t_AD
BANK
t_AD
L
t_AD
Row
t_AD
Row
t_CSD ^tCSD ^tCSD
t_RWD
t_RWD
t_AD
L
t_AD
Col
t_RASD t_RASD t_RASD t_RASD
t_AD
t_AD
t_AD
t_CSD
t_CASD
t_DQMD
t_BSD
t_CKED
t_DACD
t_DTED
t_CASD
t_CASD
t_DQMD
t_DQMD
t_RDS
t_RDH
d0
d1
d2
d3
t_BSD t_BSD
t_DACD
t_DTED
t_DACD
t_DTED
Figure 33.13 SRAM Bus Cycle in Bank Open Mode Pre-charge Read Bus Cycle
(PRE-ACT-READ)
(BOMODE[1:0]= 00, SRP[1:0]= 00, SCL[2:0]= 000, SRCD=0, IRP= 2cyc,
CAS Latency= 2cyc, IRCD= 2cyc)
Rev. 1.00 Nov. 22, 2007 Page 1592 of 1692
REJ09B0360-0100