SH7764 Datasheet, PDF (682/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Table 18.4 shows the SSI_DMAC1 register configuration. Table 18.5 shows the register state in
each operating mode.
Table 18.4 SSI_DMAC1 Register Configuration
Channel Register Name
3
DMA mode register 3
RDMA transfer source
address register 3
RDMA transfer word
count register 3
WDMA transfer
destination address
register 3
WDMA transfer word
count register 3
DMA control register 3
Transmit suspension
block counter 3
Transmit suspension
transfer data register 3
Block count source
register 3
Block counter 3
n-times block transfer
interrupt count source
register 3
n-times block counter 3
4
DMA mode register 4
RDMA transfer source
address register 4
RDMA transfer word
count register 4
WDMA transfer
destination address
register 4
Abbreviation R/W
SSIDMMR3 R/W
SSIRDMADR3 R/W
SSIRDMCNTR3 R/W
SSIWDMADR3 R/W
SSIWDMCNTR3 R/W
SSIDMCOR3 R/W
SSISTPBLCNT3 R/W
SSISTPDR3 R/W
SSIBLCNTSR3 R/W
SSIBLCNT3 R
SSIBLNCNTSR3 R/W
SSIBLNCNT3 R
SSIDMMR4 R/W
SSIRDMADR4 R/W
SSIRDMCNTR4 R/W
SSIWDMADR4 R/W
Area P4
Address
H'FF50 1000
H'FF50 1008
H'FF50 1010
H'FF50 1018
H'FF50 1020
H'FF50 1028
H'FF50 1030
H'FF50 1038
H'FF50 1040
H'FF50 1048
H'FF50 1050
H'FF50 1058
H'FF50 1060
H'FF50 1068
H'FF50 1070
H'FF50 1078
Area 7
Address
Access
Size
H'1F50 1000 32
H'1F50 1008 32
H'1F50 1010 32
H'1F50 1018 32
H'1F50 1020 32
H'1F50 1028 32
H'1F50 1030 32
H'1F50 1038 32
H'1F50 1040 32
H'1F50 1048 32
H'1F50 1050 32
H'1F50 1058 32
H'1F50 1060 32
H'1F50 1068 32
H'1F50 1070 32
H'1F50 1078 32
Rev. 1.00 Nov. 22, 2007 Page 626 of 1692
REJ09B0360-0100