SH7764 Datasheet, PDF (1357/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
0
TRINTE0 0
R/W FLDTFIFO Transfer Request Enable to CPU
Enables or disables an interrupt request to the CPU by
a transfer request issued from FLDTFIFO.
0: Disables an interrupt request to the CPU by a
transfer request from FLDTFIFO
1: Enables an interrupt request to the CPU by a transfer
request from FLDTFIFO
When the DMA transfer is enabled, this bit should be
cleared to 0.
25.3.9 Ready Busy Timeout Setting Register (FLBSYTMR)
FLBSYTMR is a 32-bit readable/writable register that specifies the timeout time when the FR/B
pin is busy.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————
RBTMOUT[19:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RBTMOUT[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
31 to 20 —
Initial
Value R/W
All 0 R
19 to 0 RBTMOUT[19:0] H'00000 R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Ready Busy Timeout
Specify timeout time (the number of Pck clocks) in
busy state. When these bits are set to 0, timeout is
not generated.
Rev. 1.00 Nov. 22, 2007 Page 1301 of 1692
REJ09B0360-0100