SH7764 Datasheet, PDF (52/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 21.22
Table 21.23
Table 21.24
Table 21.25
Table 21.26
Table 21.27
Table 21.28
Table 21.29
Table 21.30
Table 21.31
Buffer Memory Map......................................................................................... 973
Relationship between Transfer Mode Settings by CNTMD Bit and
Timings at which Reading Data or Transmitting Data from FIFO Buffer is
Enabled ............................................................................................................. 975
FIFO Port Function Settings ............................................................................. 977
FIFO Port Access Categorized by Pipe............................................................. 977
Packet Reception and Buffer Memory Clearing Processing............................. 979
NYET Handshake Responses ........................................................................... 984
Error Detection when a Token is Received ...................................................... 987
Error Detection when a Data Packet is Received.............................................. 988
Functions of the Interval Counter when the Function Controller Function is
Selected............................................................................................................. 989
Conditions for Generating a Transaction .......................................................... 998
Section 22 LCD Controller (LCDC)
Table 22.1 Pin Configuration................................................................................................ 1003
Table 22.2 Register Configuration........................................................................................ 1004
Table 22.3 Register State in Each Operating Mode.............................................................. 1005
Table 22.4 I/O Clock Frequency and Clock Division Ratio ................................................. 1008
Table 22.5 Available Power-Supply Control-Sequence Periods at Typical Frame Rates..... 1047
Table 22.6 LCDC Operating Modes..................................................................................... 1048
Table 22.7 LCD Module Power-Supply States..................................................................... 1048
Section 23 G2D
Table 23.1 Commands and Rendering Attributes ................................................................. 1065
Table 23.2 Commands and Rendering Attributes. ................................................................ 1067
Table 23.3 Setting Ranges of Parameters Set by Registers and Saturation Processing ........ 1075
Table 23.4 Vertex Ranges after Operation and Saturation Processing ................................. 1075
Table 23.5 Register Configuration........................................................................................ 1184
Table 23.6 Register Bit Configuration.................................................................................. 1187
Table 23.7 Initial Register Values at Hardware Reset and Software Reset .......................... 1189
Section 24 Video Display Controller (VDC2)
Table 24.1 Pin Configuration................................................................................................ 1223
Table 24.2 Functional Blocks in VDC2................................................................................ 1224
Table 24.3 Register Configuration in Graphics Block 1....................................................... 1234
Table 24.4 Register Configuration in Graphics Block 2....................................................... 1235
Table 24.5 Register Configuration in Graphics Block 3....................................................... 1236
Table 24.6 Register Configuration in Graphics Block 4....................................................... 1237
Table 24.7 Register Configuration in Display Control Block............................................... 1238
Table 24.8 Functions of Display Enable Bits ....................................................................... 1240
Table 24.9 α Value and Blending Ratio ............................................................................... 1250
Rev. 1.00 Nov. 22, 2007 Page lii of lvi