SH7764 Datasheet, PDF (662/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.12 DMA Transfer Count Register (ATAPI_DMA_TRANS_CNT)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
DTRC[28:16]
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DTRC[15:1]
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Initial
Bit
Bit Name
Value
R/W Description
31 to 29 —
All 0
R
Reserved
28 to 1 DTRC[28:1] 0
R/W DTRC sets the DMA transfer count.
Bits 28 to 0 are used to set the DMA transfer
count on a byte basis.
Bit 0 is ignored because the ATAPI data bus is
handled on a 16-bit basis (on a word basis).
0
—
0
R
Reserved
Note: This count value does not change and the set value is retained even after DMA activation.
Rev. 1.00 Nov. 22, 2007 Page 606 of 1692
REJ09B0360-0100