SH7764 Datasheet, PDF (1294/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
Table 24.7 Register Configuration in Display Control Block
Register Name
Abbreviation
P4 Area
R/W Address*
Area 7
Address*
Access
Size
SG mode register
SGMODE
R/W H'FFEB 0000 H'1FEB 0000 32, 16, or 8
Interrupt output control SGINTCNT
register
R/W H'FFEB 0004 H'1FEB 0004 32, 16, or 8
Sync signal control
register
SYNCNT
R/W H'FFEB 0008 H'1FEB 0008 32, 16, or 8
External sync signal
input timing control
register
EXTSYNCNT
R/W H'FFEB 000C H'1FEB 000C 32, 16, or 8
Reserved

R
H'FFEB 0100 H'1FEB 0100 32, 16, or 8
Sync signal size register SYNSIZE
R/W H'FFEB 0104 H'1FEB 0104 32, 16, or 8
Vertical sync signal
VSYNCTIM
timing control register
R/W H'FFEB 0108 H'1FEB 0108 32, 16, or 8
Horizontal sync signal HSYNCTIM
timing control register
R/W H'FFEB 010C H'1FEB 010C 32, 16, or 8
Gate clock signal timing CLSTIM
control register
R/W H'FFEB 0110 H'1FEB 0110 32, 16, or 8
Sampling start signal SPLTIM
timing control register
R/W H'FFEB 0118 H'1FEB 0118 32, 16, or 8
Gate control signal
COMTIM
timing control register
R/W H'FFEB 011C H'1FEB 011C 32, 16, or 8
SGDE area start
position register
SGDESTART
R/W H'FFEB 0120 H'1FEB 0120 32, 16, or 8
SGDE area size register SGDESIZE
R/W H'FFEB 0124 H'1FEB 0124 32, 16, or 8
CDE chroma-key color CDECRKY
register
R/W H'FFEB 0128 H'1FEB 0128 32, 16, or 8
Reserved

R
H'FFEB 0148 H'1FEB 0148 32, 16, or 8
T-1004 control register T1004CNT
R/W H'FFEB 0200 H'1FEB 0200 32, 16, or 8
T-1004 video start
position register
T1004OFFSET R/W H'FFEB 0204 H'1FEB 0204 32, 16, or 8
Reserved

R
H'FFEB 0208 H'1FEB 0208 32, 16, or 8
Reserved

R
H'FFEB 020C H'1FEB 020C 32, 16, or 8
Note: * Use a P4 area address to access a register in the P4 area in the virtual address space.
Use an area 7 address to access a register from area 7 in the physical address space
through the TLB.
Rev. 1.00 Nov. 22, 2007 Page 1238 of 1692
REJ09B0360-0100