SH7764 Datasheet, PDF (511/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.4 Interrupt Sources
There are three types of interrupt sources: NMI, IRQ, and on-chip modules. Each interrupt has a
priority level (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is set,
the interrupt is masked and interrupt requests are ignored.
13.4.1 NMI Interrupt
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in
SR of the CPU is set to 1. In sleep mode, the interrupt is accepted even if the BL bit is set to 1.
A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input
from the NMI pin is edge-detected. The NMI edge select bit (NMIE) in ICR0 is used to select
either rising or falling edge as the detection edge. When the NMIE bit in ICR0 is modified, the
NMI interrupt is not detected for a maximum of six bus clock cycles after the modification. The
IMASK value in SR is not affected by the accepted NMI interrupt.
13.4.2 IRQ Interrupts
The IRQnS[1:0] (n = 0, 1) bits in ICR1 is used to select either rising edge, falling edge, low level
or high level detection.
A priority level (from 15 to 0) can be set for each input by writing to INTPRI.
When detects the IRQ interrupt request by low level or high level, the IRQ interrupt pin input
level should be held until the CPU accepts the interrupt and starts interrupt exception handling.
When high or low level detection is selected, once the interrupt request has been detected, the
INTC holds the interrupt request as the interrupt source in INTREQ even if the IRQ interrupt pin
level may be changed and canceled. The interrupt source is being held until the CPU accepts any
interrupt request (IRQ or not) or the corresponding interrupt mask bit is set to 1. Then clear the
interrupt source that held in INTREQ after clearing the interrupt request in the exception handling
routine. For details of clearing the interrupt request, see section 13.7.3, To Clear IRQ Interrupt
Requests.
When the INTMU bit in CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is
automatically modified to the level of the accepted interrupt. When the INTMU bit is cleared to 0,
the IMASK value in SR is not affected by the accepted interrupt.
Rev. 1.00 Nov. 22, 2007 Page 455 of 1692
REJ09B0360-0100