SH7764 Datasheet, PDF (20/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

18.3.10 Block Counters 0 to 5 (SSIBLCNT0 to SSIBLCNT5) ......................................... 652
18.3.11 n-Times Block Transfer Interrupt Count Source Registers 0 to 5
(SSIBLNCNTSR0 to SSIBLNCNTSR5).............................................................. 652
18.3.12 n-Times Block Counters 0 to 5 (SSIBLNCNT0 to SSIBLNCNT5) ..................... 653
18.3.13 DMA Operation Registers 0 and 1 (SSIDMAOR0 and SSIDMAOR1) ............... 654
18.3.14 Interrupt Status Registers 0 and 1 (SSIDMINTSR0 and SSIDMINTSR1)........... 656
18.3.15 Interrupt Mask Registers 0 and 1 (SSIDMINTMR0 and SSIDMINTMR1)......... 661
18.3.16 Control Registers 0 to 5 (SSICR0 to SSICR5) ..................................................... 664
18.3.17 Status Registers 0 to 5 (SSISR0 to SSISR5)......................................................... 671
18.3.18 Transmit Data Registers 0 to 5 (SSITDR0 to SSITDR5) ..................................... 677
18.3.19 Receive Data Registers 0 to 5 (SSIRDR0 to SSIRDR5)....................................... 677
18.4 Operation ........................................................................................................................... 678
18.4.1 Operation of SSI_CLKSEL .................................................................................. 678
18.4.2 Operation of SSI_DMAC0 and SSI_DMAC1 ...................................................... 678
18.4.3 Operation of SSI_CH0 to SSI_CH5 ..................................................................... 680
18.5 Usage Note......................................................................................................................... 698
18.5.1 Restrictions when an Overflow Occurs during Receive DMA Operation ............ 698
18.5.2 Restrictions during Operation in Slave Mode....................................................... 698
18.5.3 Restrictions when Specify Each Register ............................................................. 698
Section 19 Ethernet Controller (EtherC) ........................................................... 701
19.1 Features.............................................................................................................................. 701
19.2 Input/Output Pins............................................................................................................... 702
19.3 Register Descriptions......................................................................................................... 703
19.3.1 EtherC Mode Register (ECMR)............................................................................ 705
19.3.2 EtherC Status Register (ECSR) ............................................................................ 709
19.3.3 EtherC Interrupt Permission Register (ECSIPR) .................................................. 711
19.3.4 PHY Interface Register (PIR) ............................................................................... 712
19.3.5 MAC Address High Register (MAHR) ................................................................ 713
19.3.6 MAC Address Low Register (MALR) ................................................................. 714
19.3.7 Receive Frame Length Register (RFLR) .............................................................. 715
19.3.8 PHY Status Register (PSR)................................................................................... 716
19.3.9 Transmit Retry Over Counter Register (TROCR) ................................................ 717
19.3.10 Delayed Collision Detect Counter Register (CDCR)............................................ 718
19.3.11 Lost Carrier Counter Register (LCCR)................................................................. 719
19.3.12 Carrier Not Detect Counter Register (CNDCR) ................................................... 720
19.3.13 CRC Error Frame Receive Counter Register (CEFCR)........................................ 721
19.3.14 Frame Receive Error Counter Register (FRECR)................................................. 722
19.3.15 Too-Short Frame Receive Counter Register (TSFRCR) ...................................... 723
19.3.16 Too-Long Frame Receive Counter Register (TLFRCR) ...................................... 724
Rev. 1.00 Nov. 22, 2007 Page xx of lvi