SH7764 Datasheet, PDF (1271/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 G2D
operations (16-bit integer portion and 16-bit fractional portion), MTRDR should be set within the
range of −2¹⁵ ≤ MTRDR < 2¹⁵.
MTRDR retains its value at a reset.
Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate
Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions.
(6) Matrix Parameter E Register (MTRER)
Offset:
H'114
Initial Value: Undefined
The matrix parameter E register (MTRER) is a 32-bit readable/writable register which specifies a
matrix parameter at coordinate change in the single-precision floating-point format defined by the
IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point
operations (16-bit integer portion and 16-bit fractional portion), MTRER should be set within the
range of −2¹⁵ ≤ MTRER < 2¹⁵.
MTRER retains its value at a reset.
Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate
Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions.
(7) Matrix Parameter F Register (MTRFR)
Offset:
H'118
Initial Value: Undefined
The matrix parameter F register (MTRFR) is a 32-bit readable/writable register which specifies a
matrix parameter at coordinate change in the single-precision floating-point format defined by the
IEEE 754 standard. However, since internal computation is carried out with 32-bit fixed-point
operations (16-bit integer portion and 16-bit fractional portion), MTRFR should be set within the
range of −2¹⁵ ≤ MTRFR < 2¹⁵.
MTRFR retains its value at a reset.
Note: For details on the setting range, see (2) 4 × 4 Matrix Operation, to (5) Coordinate
Transformation Flow and Saturation Processing, in section 23.1.2, Basic Functions.
Rev. 1.00 Nov. 22, 2007 Page 1215 of 1692
REJ09B0360-0100