SH7764 Datasheet, PDF (186/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
other exceptions is determined depending on the processing mode by SR after restoring or
the BL bit. The completion type exception is accepted before branching to the destination
of RTE instruction. However, if the re-execution type exception is occurred, the operation
cannot be guaranteed.
B. The user break is not accepted by the instruction in the delay slot of the RTE instruction.
(5) Changing the SR Register Value and Accepting Exception
A. When the MD or BL bit in the SR register is changed by the LDC instruction, the
acceptance of the exception is determined by the changed SR value, starting from the next
instruction.* In the completion type exception, an exception is accepted after the next
instruction has been executed. However, an interrupt of completion type exception is
accepted before the next instruction is executed.
Note: * When the LDC instruction for SR is executed, following instructions are fetched again
and the instruction fetch exception is evaluated again by the changed SR.
Rev. 1.00 Nov. 22, 2007 Page 130 of 1692
REJ09B0360-0100