SH7764 Datasheet, PDF (1486/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Watchdog Timer and Reset
29.3.2 Watchdog Timer Control/Status Register (WDTCSR)
WDTCSR is a readable/writable 32-bit register that comprises the timer mode-selecting bit and
overflow flags. Use a longword access to write to the WDTCSR, with H'A5 in the bits 31 to 24.
The reading value of bits 31 to 24 is always H'00.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
(Given code)

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
        TME WT/IT  WOVF IOVF   
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R R/W R/W R R R
Initial
Bit
Bit Name Value R/W
31 to 24 (Given
code)
H'00 R/W
23 to 8 
All 0 R
7
TME
0
R/W
6
WT/IT
0
R/W
Description
Reserved (Given code for writing)
These bits are always read as H'00. To write to this
register, the write value must be H'A5.
Reserved
These bits are always read as 0. The write value
should always be 0.
Timer Enable
Specifies starting and stopping of timer operation.
0: Stops counting up
1: Starts counting up
Timer Mode Select
Specifies whether the WDT is used as a watchdog
timer or interval timer. Up counting may not be
performed correctly if this bit is modified while the
WDT is running.
0: Interval timer mode
1: Watchdog timer mode
Rev. 1.00 Nov. 22, 2007 Page 1430 of 1692
REJ09B0360-0100