SH7764 Datasheet, PDF (660/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 17 ATAPI
17.3.10 Descriptor DMA Transfer Count
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
———
DDTRC[28:16]
Initial value: ₀
0
0 —————————————
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DDTRC[15:1]
—
Initial value: — — — — — — — — — — — — — — — 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
The descriptor DMA transfer count should be set in the descriptor table base address + "m" in the
memory, where the value of m is any multiple number of 2 plus 1 (such as 1, 3, 5, …).
Bit
Bit Name
Initial Value R/W
31 to 29 —
All 0
R
28 to 1 DDTRC[28:1] Undefined R/W
0
—
0
R
Description
Reserved
These bits set the DMA transfer count during
descriptor operation.
Bits 28 to 0 are used to set the DMA transfer
count on a byte basis.
Bit 0 is ignored because the ATAPI data bus is
handled on a 16-bit basis (on a word basis).
Reserved
Rev. 1.00 Nov. 22, 2007 Page 604 of 1692
REJ09B0360-0100