SH7764 Datasheet, PDF (1485/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Watchdog Timer and Reset
29.3.1 Watchdog Timer Stop Time Register (WDTST)
WDTST is a readable/writable 32-bit register that specifies the time until a watchdog timer
overflows. The time until WDTCNT overflows becomes the minimum value when set H'001 to
the bits 11 to 0, and the maximum value when set H'000 to the bits 11 to 0. Use a longword access
to write to the WDTST, with H'5A in the bits 31 to 24. The reading value of bits 31 to 24 is
always H'00.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
(Given code)

Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0

WDTST
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 24 (Given
code)
H'00 R/W
23 to 12 
All 0 R
11 to 0 WDTST All 0 R/W
Description
Reserved (Given code for writing)
These bits are always read as H'00. To write to this
register, the write value must be H'5A.
Reserved
These bits are always read as 0. The write value
should always be 0.
Counter value
Rev. 1.00 Nov. 22, 2007 Page 1429 of 1692
REJ09B0360-0100