SH7764 Datasheet, PDF (767/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Ethernet Controller (EtherC)
19.3.3 EtherC Interrupt Permission Register (ECSIPR)
ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources
indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
—
—
BFSIPR
PFRO
IP
—
LCHN
GIP
MPDIP
ICDIP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 6 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
BFSIPR 0
R/W Continuous Broadcast Frame Reception Interrupt
Enable
0: Enables an interrupt requested by the BFR bit in
ECSR
1: Disables an interrupt requested by the BFR bit in
ECSR
4
PFROIP 0
R/W PAUSE Frame Retransmit Interrupt Enable
0: Interrupt notification by the PFROI bit is disabled
1: Interrupt notification by the PFROI bit is enabled
3

0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
LCHNGIP 0
R/W LINK Signal Change Interrupt Enable
0: Interrupt notification by the LCHNG bit is disabled
1: Interrupt notification by the LCHNG bit is enabled
Rev. 1.00 Nov. 22, 2007 Page 711 of 1692
REJ09B0360-0100