SH7764 Datasheet, PDF (460/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
Figure 12.17 shows the timing of the DTEND output.
CLKOUT
Bus cycle
DMAC
Last DMA transfer
CPU
DMAC
CPU
CPU
DREQ
DACK
(High-active)
DTEND
(High-active)
Figure 12.17 DMA Transfer End Signal (Cycle Steal Mode Level Detection)
Note that the DACK output and DTEND output are divided to align the data when an 8-bit or 16-
bit external device is accessed in longword units, or when an 8-bit external device is accessed in
word units. This example is shown in figure 12.18.
Rev. 1.00 Nov. 22, 2007 Page 404 of 1692
REJ09B0360-0100