SH7764 Datasheet, PDF (494/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 Interrupt Controller (INTC)
13.3.13 Interrupt Source Register 11 (Mask State is affected) (INT2A11)
INT2A11 (mask state is affected) is a 32-bit read-only register that indicates interrupt source
modules. Note that if interrupt masking is set in the interrupt mask register, INT2A11 does not
indicate a source module in a corresponding bit. To check whether interrupts are generated,
regardless of the state of the interrupt mask register, use INT2A01.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
— SCIF2 —
—
—
—
— VDC2 — USB EtherC
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
— LCDC —
—
IIC
—
SRC SRC
ODFI IDEI
—
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
31 to 26 —
All 0
25
SCIF2 0
24 to 20 —
All 0
19
VDC2
0
18
—
0
17
USB
0
16
EtherC 0
15 to 8 —
All 0
7
LCDC 0
6, 5
—
All 0
4
IIC
0
R/W Function
Description
R
Reserved
Indicates interrupt
These bits are always read as 0. ^{sources for each}
peripheral module
R
Indicates SCIF2 interrupt source _{(INT2A11 is affected by}
R
Reserved
the state of the interrupt
These bits are always read as 0. ^{mask register).}
0: No interrupts
R
Indicates VDC2 interrupt source
1: Interrupts are
R
Reserved
generated
This bit is always read as 0.
Note: Reading the
R
Indicates USB interrupt source
INTEVT code
R
Indicates EtherC interrupt
source
R
Reserved
notified to the
CPU directly can
identify interrupt
sources. In this
This bit is always read as 0.
R
Indicates LCDC interrupt source
case, reading
INT2A11 is not
necessary.
R
Reserved
These bits are always read as 0.
R
Indicates IIC interrupt source
Rev. 1.00 Nov. 22, 2007 Page 438 of 1692
REJ09B0360-0100