SH7764 Datasheet, PDF (688/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Table 18.7 Register State in Each Operating Mode for SSI_CH0 to SSI_CH5
Channel Register Name
Power-On
Abbreviation Reset
0
Control register 0
SSICR0
H'0000 0000
Status register 0
SSISR0
H'0210 A003
Transmit data register 0 SSITDR0
H'0000 0000
Receive data register 0 SSIRDR0
H'0000 0000
1
Control register 1
SSICR1
H'0000 0000
Status register 1
SSISR1
H'0210 A003
Transmit data register 1 SSITDR1
H'0000 0000
Receive data register 1 SSIRDR1
H'0000 0000
2
Control register 2
SSICR2
H'0000 0000
Status register 2
SSISR2
H'0210 A003
Transmit data register 2 SSITDR2
H'0000 0000
Receive data register 2 SSIRDR2
H'0000 0000
3
Control register 3
SSICR3
H'0000 0000
Status register 3
SSISR3
H'0210 A003
Transmit data register 3 SSITDR3
H'0000 0000
Receive data register 3 SSIRDR3
H'0000 0000
4
Control register 4
SSICR4
H'0000 0000
Status register 4
SSISR4
H'0210 A003
Transmit data register 4 SSITDR4
H'0000 0000
Receive data register 4 SSIRDR4
H'0000 0000
5
Control register 5
SSICR5
H'0000 0000
Status register 5
SSISR5
H'0210 A003
Transmit data register 5 SSITDR5
H'0000 0000
Receive data register 5 SSIRDR5
H'0000 0000
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev. 1.00 Nov. 22, 2007 Page 632 of 1692
REJ09B0360-0100