SH7764 Datasheet, PDF (851/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 20 Ethernet Controller Direct Memory Access Controller (E-DMAC)
20.3.2 Transmission
When the transmit request bit (TR) in the E-DMAC transmit request register (EDTRR) is set while
the transmission function is enabled, the E-DMAC reads the descriptor following the previously
used descriptor from the transmit descriptor list (or the descriptor indicated by the transmit
descriptor start address register (TDLAR) at the initial start time). If the TACT bit of the read
descriptor is set to 1 (valid), the E-DMAC sequentially reads transmit frame data from the transmit
buffer start address specified by TD2 for transfer to the EtherC. The EtherC creates a transmit
frame and starts transmission to the MII. After DMA transfer of data equivalent to the buffer
length specified in the descriptor, the following processing is carried out according to the TFP
value.
1. TFP = 00 or 10 (frame continuation):
Descriptor write-back (writing 0 to the TACT bit) is performed after DMA transfer.
2. TFP = 01 or 11 (frame end):
Descriptor write-back (writing 0 to the TACT bit and writing status) is performed after
completion of frame transmission.
As long as the TACT bit of a read descriptor is set to 1 (valid), the reading of E-DMAC
descriptors and the transmission of frames continue. When a descriptor with the TACT bit cleared
to 0 (invalid) is read, the E-DMAC clears the TR bit in EDTRR to 0 and completes transmit
processing.
Rev. 1.00 Nov. 22, 2007 Page 795 of 1692
REJ09B0360-0100