SH7764 Datasheet, PDF (37/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figure 15.8 Sample Flowchart for Receiving Serial Data (cont)................................................... 538
Figure 15.9 Example of SCIF Receive Operation (8-Bit Data, Parity, 1 Stop Bit) ....................... 540
Figure 15.10 Example of Operation Using Modem Control (RTS) .............................................. 540
Figure 15.11 Data Format in Clock Synchronous Communication............................................... 541
Figure 15.12 Sample Flowchart for SCIF Initialization ................................................................ 543
Figure 15.13 Sample Flowchart for Transmitting Serial Data....................................................... 544
Figure 15.14 Example of SCIF Transmit Operation...................................................................... 545
Figure 15.15 Sample Flowchart for Receiving Serial Data (1)...................................................... 546
Figure 15.16 Sample Flowchart for Receiving Serial Data (2)...................................................... 546
Figure 15.17 Example of SCIF Receive Operation ....................................................................... 547
Figure 15.18 Sample Flowchart for Transmitting/Receiving Serial Data...................................... 548
Figure 15.19 Receive Data Sampling Timing in Asynchronous Mode
(Operation on a Base Clock with a Frequency 16 Times the Bit Rate) ................... 552
Section 16 I²C Bus Interface (IIC)
Figure 16.1 Block Diagram for I²C Bus Interface ......................................................................... 555
Figure 16.2 I²C Bus Timing .......................................................................................................... 574
Figure 16.3 Master Data Transmit Format .................................................................................... 575
Figure 16.4 Master Data Receive Format...................................................................................... 575
Figure 16.5 Combination Transfer Format of Master Transfer ..................................................... 576
Figure 16.6 10-Bit Address Data Transmit Format ....................................................................... 576
Figure 16.7 10-Bit Address Data Receive Format......................................................................... 577
Figure 16.8 10-Bit Address Transmit/Receive Combined Format ................................................ 577
Figure 16.9 Data Transmit Mode Operation Timing ..................................................................... 579
Figure 16.10 Data Receive Mode Operation Timing .................................................................... 581
Section 17 ATAPI
Figure 17.1 ATAPI Block Diagram............................................................................................... 587
Figure 17.2 PIO Timing Register .................................................................................................. 598
Figure 17.3 Multiword DMA Timing Register ............................................................................. 599
Figure 17.4 Ultra DMA Timing Register ...................................................................................... 600
Figure 17.5 ATAPI Data Bus Alignment ...................................................................................... 610
Figure 17.6 Procedure in PIO Transfer Mode ............................................................................... 612
Figure 17.7 Transfer to and from Memory via Pixel Bus by Polling ............................................ 614
Figure 17.8 Transfer to and from Memory via Pixel Bus by Interrupt .......................................... 615
Figure 17.9 Transfer to and from Memory via Pixel Bus by Polling ............................................ 616
Figure 17.10 Transfer to and from Memory via Pixel Bus by Interrupt ........................................ 617
Figure 17.11 Procedure in Hardware Reset for ATAPI Device .................................................... 617
Section 18 Serial Sound Interface (SSI)
Figure 18.1 Block Diagram of SSI ................................................................................................ 620
Figure 18.2 Philips Format (with no Padding) .............................................................................. 681
Rev. 1.00 Nov. 22, 2007 Page xxxvii of lvi