SH7764 Datasheet, PDF (1385/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 Sampling Rate Converter (SRC)
Bit
11 to 7
Bit Name
IFDN[4:0]
6, 5

4
FLF
3

2
OVF
Initial
Value
All 0
All 0
0
0
0
R/W Description
R
Input FIFO Data Count
Indicates the number of data units in the input FIFO.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Flush Processing Status Flag
Indicates whether flush processing is in progress or
not.
[Clearing conditions]
• When flush processing has been completed.
• When 1 has been written to the CL bit in
SRCCTRL.
[Setting condition]
• When 1 has been written to the FL bit in
SRCCTRL.
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/(W)* Output Data FIFO Overwrite Interrupt Request Flag
Indicates that the sampling rate conversion for the
next data has been completed when there are eight
units of data in the output FIFO. The sampling rate
conversion stops until the output data FIFO becomes
not full after the SRC output data register (SRCOD)
has been read.
[Clearing condition]
• When 0 has been written to the OVF bit after
reading OVF = 1.
• When 1 has been written to the CL bit in
SRCCTRL.
[Setting condition]
• When the sampling rate conversion for the next
data has been completed when there are eight
units of data in the output FIFO.
Rev. 1.00 Nov. 22, 2007 Page 1329 of 1692
REJ09B0360-0100