SH7764 Datasheet, PDF (706/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Bit
31 to 0
Initial
Bit Name Value
TXSTOPBL All 0
[31:0]
R/W Description
R/W Transfer Block Count till Transmit Suspension State
These bits set the number of blocks to be transferred
after the TXSTOP0 to TXSTOP5 bits in SSIDMAOR0
and SSIDMAOR1 are set to 1 until the transmit
suspension state is entered. Setting value is readable
during reading. (enable to read counter value)
18.3.8 Transmit Suspension Transfer Data Registers 0 to 5 (SSISTPDR0 to SSISTPDR5)
SSISTPDR0 to SSISTPDR5 is a 32-bit readable/writable register that set data to be transferred to
SSI_CH0 through SSI_CH5 during transmit suspension state other than the port function. In
transmit suspension state, data set in SSISTPDR0 to SSSISTPDR5 instead of transmit FIFO
buffers is sent to SSI_CH0 to SSI_CH5. This register value is initialized when either of the
conditions is implemented such as hardware reset, software reset or software reset for SSI_DMAC
(DMRST bit in SSIDMACOR0 to SSIDMACOR3). To be written to this register, DMEN bit in
SSIDMCOR0 to SSDMCOR5 must be 0.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TXSTOPD[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
TXSTOPD[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Initial
Bit Name Value R/W
TXSTOPD All 0 R/W
[31:0]
Description
Transfer Data during Transmit Suspension State
These bits set data to be transferred to SSI_CH0
through SSI_CH5 during transmit suspension state.
Rev. 1.00 Nov. 22, 2007 Page 650 of 1692
REJ09B0360-0100