SH7764 Datasheet, PDF (1084/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 22 LCD Controller (LCDC)
22.3.16 LCDC Power Management Mode Register (LDPMMR)
LDPMMR controls the power supply circuit that provides power to the LCD module. The usage
of two types of power-supply control pins, LCD_VCPWC and LCD_VEPWC, and turning on or
off the power supply function are selected.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ONC[3:0]
OFFD[3:0]
 VCPE VEPE DONE 

LPS[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R
R
R
R
Bit
Bit Name
15 to 12 ONC[3:0]
11 to 8 OFFD[3:0]
7

Initial Value R/W
0000
R/W
0000
R/W
0
R
Description
LCDC Power-On Sequence Period
Set the period from LCD_VEPWC assertion to
LCD_DON assertion in the power-on sequence of
the LCD module in frame units.
Specify to the value of (the period) -1.
This period is the (c) period in figures 22.4 to 22.7,
Power-Supply Control Sequence and States of the
LCD Module. For details on setting this register, see
table 22.5, Available Power-Supply Control-
Sequence Periods at Typical Frame Rates. (The
setting method is common for ONA, ONB, OFFD,
OFFE, and OFFF.)
LCDC Power-Off Sequence Period
Set the period from LCD_DON negation to
LCD_VEPWC negation in the power-off sequence
of the LCD module in frame units.
Specify to the value of (the period) -1.
This period is the (d) period in figures 22.4 to 22.7,
Power-Supply Control Sequence and States of the
LCD Module.
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 1028 of 1692
REJ09B0360-0100