SH7764 Datasheet, PDF (1350/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 NAND Flash Memory Controller (FLCTL)
25.3.6 Data Counter Register (FLDTCNTR)
FLDTCNTR is a 32-bit readable/writable register that specifies the number of bytes to be read or
written in command access mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECFLW[7:0]
DTFLW[7:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————
DTCNT[11:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
31 to 24 ECFLW[7:0] H'00
23 to 16 DTFLW[7:0] H'00
15 to 12 —
All 0
R/W Description
R FLECFIFO Access Count
Specify the number of longwords in FLECFIFO to be read
or written. These bit values are used when the CPU reads
from or writes to FLECFIFO.
In FLECFIFO read, these bits specify the number of
longwords of the data that can be read from FLECFIFO.
In FLECFIFO write, these bits specify the number of
longwords of unoccupied area that can be written in
FLECFIFO.
R FLDTFIFO Access Count
Specify the number of longwords in FLDTFIFO to be read
or written. These bit values are used when the CPU reads
from or writes to FLDTFIFO.
In FLDTFIFO read, these bits specify the number of
longwords of the data that can be read from FLDTFIFO.
In FLDTFIFO write, these bits specify the number of
longwords of unoccupied area that can be written in
FLDTFIFO.
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 1294 of 1692
REJ09B0360-0100