SH7764 Datasheet, PDF (33/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Figures
Section 1 Overview
Figure 1.1 Block Diagram ............................................................................................................... 13
Figure 1.2 Pin Arrangement ............................................................................................................ 14
Figure 1.3 Physical Address Space (1) ............................................................................................ 28
Figure 1.3 Physical Address Space (2) ............................................................................................ 29
Section 2 Programming Model
Figure 2.1 Data Formats .................................................................................................................. 31
Figure 2.2 CPU Register Configuration in Each Processing Mode................................................. 35
Figure 2.3 General Registers ........................................................................................................... 36
Figure 2.4 Floating-Point Registers................................................................................................. 38
Figure 2.5 Relationship between SZ bit and Endian........................................................................ 44
Figure 2.6 Formats of Byte Data and Word Data in Register.......................................................... 46
Figure 2.7 Data Formats in Memory ............................................................................................... 47
Figure 2.8 Processing State Transitions........................................................................................... 48
Section 4 Pipelining
Figure 4.1 Basic Pipelines ............................................................................................................... 71
Figure 4.2 Instruction Execution Patterns (1).................................................................................. 73
Figure 4.2 Instruction Execution Patterns (2).................................................................................. 74
Figure 4.2 Instruction Execution Patterns (3).................................................................................. 75
Figure 4.2 Instruction Execution Patterns (4).................................................................................. 76
Figure 4.2 Instruction Execution Patterns (5).................................................................................. 77
Figure 4.2 Instruction Execution Patterns (6).................................................................................. 78
Figure 4.2 Instruction Execution Patterns (7).................................................................................. 79
Figure 4.2 Instruction Execution Patterns (8).................................................................................. 80
Figure 4.2 Instruction Execution Patterns (9).................................................................................. 81
Section 5 Exception Handling
Figure 5.1 Instruction Execution and Exception Handling............................................................ 105
Figure 5.2 Example of General Exception Acceptance Order....................................................... 106
Section 6 Floating-Point Unit (FPU)
Figure 6.1 Format of Single-Precision Floating-Point Number..................................................... 132
Figure 6.2 Format of Double-Precision Floating-Point Number ................................................... 132
Figure 6.3 Single-Precision NaN Bit Pattern................................................................................. 135
Figure 6.4 Floating-Point Registers............................................................................................... 138
Figure 6.5 Relation between SZ Bit and Endian ........................................................................... 141
Rev. 1.00 Nov. 22, 2007 Page xxxiii of lvi