SH7764 Datasheet, PDF (1286/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.5.3 External Sync Mode
External sync mode outputs the graphic images with synchronizing the vertical or the horizontal
sync signal that are from the external sync signal generating circuit such as TV or video. Inputs
the vertical sync signal, the horizontal sync signal or the clock to corresponding pins,
EX_VSYNC, EX_HSYNC or DCLKIN.
Set up the registers related to the sync signals as follows.
(1) Setting up External Sync Mode
Set the SYNC_SEL bit to 1 in SGMODE register in order to make the external sync mode. If
the electrode of input vertical/horizontal signal is negative, reverse the input data with setting
the EX_V_TYPE bit to 1 and the EX_H_TYPE bit to 1 in SYNCNT register.
(2) Setting up Output for COM/CDE Pins
Set the COM_CDE_SEL bit to 1 and the CDE_EXE bit to 1 in SGMODEA register, and
output CDE signal to the COM/CDE pins. Assert the CDE signal only if the signal
corresponds to the target color of chroma-keying setting in the CDECRKY register. The
COM_TYPE bit in SYNCNT controls the electrode of CDE signal.
(3) Setting up Timing for Input and Output
Set up the sampling timing for vertical/horizontal signal which is input data and the output
timing for RGB data and CDE signal which are output data with DCLKIN rising or falling
according to the specifications of the display as an external sync signal generating circuit.
(refer to the SYNCNT register)
VDC2 wait the EX_VSYNC signal staying in the vertical blanking interval until the signal
input. (Vsync does not perform self-processing.) In the same way, when the EX_HSYNC
signal is input to VDC2, VDC2 performs horizontal indicating completion and transfer to the
next processing. VDC2 wait the EX_HSYNC signal staying in the horizontal blanking interval
until the signal input. (Hsync does not perform self-processing.)
24.5.4 Digital Video Output
For the BTA T-1004 digital video output, the VDC2 generates an 8-bit luminance signal (Y),
chrominance signals (CB and CR), EAV, and SAV conforming to the BTA T-1004 (8:4:4-format
parallel bit interface) standard.
Rev. 1.00 Nov. 22, 2007 Page 1230 of 1692
REJ09B0360-0100