SH7764 Datasheet, PDF (1297/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.2 Bus Control Registers (GRCBUSCNT1 to GRCBUSCNT4)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0














 ENDIAN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R/W
Bit
31 to 1
Bit Name

Initial
Value
All 0
0
ENDIAN 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Specifies the endian for the pixel bus.
0: Little endian
1: Big endian
Pixel bus
MSB
127
16 bits
15
0
RGB7
RGB6
RGB5
128 bits
RGB4 RGB3
RGB2
RGB1
LSB
0
RGB0
R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0
Note: The image is displayed in the order of pixels (RGB0 -> RGB1 -> RGB2 -> ... -> RGB6 -> RGB7) from left to right.
Figure 24.7 Pixel Bus Endian (ENDIAN = 0)
Rev. 1.00 Nov. 22, 2007 Page 1241 of 1692
REJ09B0360-0100