SH7764 Datasheet, PDF (156/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
Initial
Bit
Bit Name Value R/W
31 to 5 
All 0 R
4
MMCAW 0
R/W
3, 2

All 0 R
1
BRDSSLP 0
R/W
0
RTEDS
0
R/W
Description
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
Memory-Mapped Cache Associative Write
0: Memory-mapped cache associative write is disabled.
(A data address error exception will occur.)
1: Memory-mapped cache associative write is enabled.
For further details, refer to section 8.6.5, Memory-
Mapped Cache Associative Write Operation.
Reserved
For details on reading/writing these bits, see General
Precautions on Handling of Product.
Delay Slot SLEEP Instruction
0: The SLEEP instruction in the delay slot is disabled.
(The SLEEP instruction is taken as a slot illegal
instruction.)
1: The SLEEP instruction in the delay slot is enabled.
RTE Delay Slot
0: An instruction other than the NOP instruction in the
delay slot of the RTE instruction is disabled. (An
instruction other than the NOP instruction is taken as
a slot illegal instruction).
1: An instruction other than the NOP instruction in the
delay slot of the RTE instruction is enabled.
Rev. 1.00 Nov. 22, 2007 Page 100 of 1692
REJ09B0360-0100