SH7764 Datasheet, PDF (711/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 18 Serial Sound Interface (SSI)
Initial
Bit
Bit Name Value R/W Description
5
TXSTOP1 0
R/W SSI_CH1 (CH4) Transmit Suspension
(TXSTOP4)
Temporarily stops the data transfer from SSI_CH1
(CH4) transmit FIFO buffer to SSI_CH1 (CH4) and
transfers data set in SSITXSTPDR1 (4) to SSI_CH1
(CH4).
0: SSI_CH1 (CH4) performs normal operation.
Data is transferred from SSI_CH1 (CH4) transmit
FIFO buffer to SSI_CH1 (CH4).
1: SSI_CH1 (CH4) temporarily stops data transfer.
Data is transferred from SSITXSTPDR1 (4) to
SSI_CH1 (CH4).
4
TXSTOP0 0
R/W SSI_CH0 (CH3) Transmit Suspension
(TXSTOP3)
Temporarily stops the data transfer from SSI_CH0
(CH3) transmit FIFO buffer to SSI_CH0 (CH3) and
transfers data set in SSITXSTPDR0 (3) to SSI_CH0
(CH3).
0: SSI_CH0 (CH3) performs normal operation.
Data is transferred from SSI_CH0 (CH3) transmit
FIFO buffer to SSI_CH0 (CH3).
1: SSI_CH0 (CH3) temporarily stops data transfer.
Data is transferred from SSITXSTPDR0 (3) to
SSI_CH0 (CH3).
3, 2

All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Nov. 22, 2007 Page 655 of 1692
REJ09B0360-0100