SH7764 Datasheet, PDF (424/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 Direct Memory Access Controller (DMAC)
12.3.4 DMA Destination Address Registers (DARB0 to DARB3)
DARB are 32-bit readable/writable registers that specify the destination address of a DMA
transfer that is set in DAR again in repeat/reload mode. Data to be written from the CPU to DAR
is also written to DARB. To set DARB address that differs from DAR address, write data to
DARB after DAR.
To transfer data in word or in longword units, specify the address with word or longword address
boundary. When transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary
must be set for the source address value. The initial value is undefined.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DARB
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DARB
Initial value: _{— — — — — — — — — — — — — — — —}
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
12.3.5 DMA Transfer Count Registers (TCR0 to TCR5)
TCR are 32-bit readable/writable registers that specify the DMA transfer count. The number of
transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and
16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers
indicate the remaining transfer count.
The upper eight bits of TCR (bits 31 to 24) are always read as 0, and the write value should always
be 0. The initial value is undefined.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TCR
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TCR
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Nov. 22, 2007 Page 368 of 1692
REJ09B0360-0100