SH7764 Datasheet, PDF (195/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Floating-Point Unit (FPU)
6.3.2 Floating-Point Status/Control Register (FPSCR)
bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FR SZ PR DN
Cause
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
R/W: R R R R R R R R R R R/W R/W R/W R/W R/W R/W
bit: 15
Initial value: 0
R/W: R/W
14 13
Cause
00
R/W R/W
12
0
R/W
11
0
R/W
10 9 8
Enable (EN)
000
R/W R/W R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
Flag
0
R/W
3
0
R/W
2
0
R/W
10
RM
01
R/W R/W
Bit
Bit Name
31 to 22 —
Initial
Value
All 0
21
FR
0
20
SZ
0
19
PR
0
18
DN
1
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Floating-Point Register Bank
0: FPR0_BANK0 to FPR15_BANK0 are assigned to
FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1
are assigned to XF0 to XF15
1: FPR0_BANK0 to FPR15_BANK0 are assigned to
XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1
are assigned to FR0 to FR15
R/W Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register
pair (64 bits)
For relations between endian and the SZ and PR bits,
see figure 6.5.
R/W Precision Mode
0: Floating-point instructions are executed as
single-precision operations
1: Floating-point instructions are executed as
double-precision operations (graphics support
instructions are undefined)
For relations between endian and the SZ and PR bits,
see figure 6.5.
R/W Denormalization Mode
0: Denormalized number is treated as such
1: Denormalized number is treated as zero
Rev. 1.00 Nov. 22, 2007 Page 139 of 1692
REJ09B0360-0100