SH7764 Datasheet, PDF (529/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Table 14.3 Register States in Each Processing Mode
Section 14 Timer Unit (TMU)
Channel Register Name
Power-on
Abbrev. Reset
Sleep
0, 1, 2 Timer output control register TOCR
Common _{Timer start register 0}
TSTR0
H'00
H'00
Retained
Retained
0
Timer constant register 0 TCOR0 H'FFFF FFFF Retained
Timer counter 0
TCNT0 H'FFFF FFFF Retained
Timer control register 0
TCR0 H'0000
Retained
1
Timer constant register 1 TCOR1 H'FFFF FFFF Retained
Timer counter 1
TCNT1 H'FFFF FFFF Retained
Timer control register 1
TCR1 H'0000
Retained
2
Timer constant register 2 TCOR2 H'FFFF FFFF Retained
Timer counter 2
TCNT2 H'FFFF FFFF Retained
Timer control register 2
TCR2 H'0000
Retained
Input capture register 2
TCPR2 Retained
Retained
3, 4, 5 Timer start register 1
Common
TSTR1 H'00
Retained
3
Timer constant register3
TCOR3 H'FFFF FFFF Retained
Timer counter 3
TCNT3 H'FFFF FFFF Retained
Timer control register 3
TCR3 H'0000
Retained
4
Timer constant register 4 TCOR4 H'FFFF FFFF Retained
Timer counter 4
TCNT4 H'FFFF FFFF Retained
Timer control register 4
TCR4 H'0000
Retained
5
Timer constant register 5 TCOR5 H'FFFF FFFF Retained
Timer counter 5
TCNT5 H'FFFF FFFF Retained
Timer control register 5
TCR5 H'0000
Retained
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Module
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Rev. 1.00 Nov. 22, 2007 Page 473 of 1692
REJ09B0360-0100