SH7764 Datasheet, PDF (1327/1752 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 24 Video Display Controller (VDC2)
24.6.25 CDE Chroma-Key Color Register (CDECRKY)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CDE_R[4:0]
CDE_G[5:0]
CDE_B[4:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 16 
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
15 to 11 CDE_R[4:0] 00000
R/W
These bits specify the R value as the target of
chroma-keying to output the CDE signal.
10 to 5 CDE_G[5:0] 000000 R/W
These bits specify the G value as the target of
chroma-keying to output the CDE signal.
4 to 0 CDE_B[4:0] 00000
R/W
These bits specify the B value as the target of
chroma-keying to output the CDE signal.
Note: After the overlay processing (layer 1 + layer 2 + layer 3 + layer 4) is applied to a graphic
image, the resultant image data is compared with the above specified color and the VDC2
outputs the CDE signal when they match (chroma-keying is not applied for each layer).
Rev. 1.00 Nov. 22, 2007 Page 1271 of 1692
REJ09B0360-0100